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M25P128
128 Mbit (Multilevel), low-voltage, Serial Flash memory with 50-MHz SPI bus interface
Feature summary

128 Mbit of Flash memory 2.7 to 3.6 V single supply voltage SPI bus compatible Serial interface 50 MHz clock rate (maximum) VPP = 9 V for fast Program/Erase mode (optional) Page Program (up to 256 Bytes): - in 2.5 ms (typical) - in 1.2 ms (typical with VPP = 9 V) Sector Erase (2 Mbit) Bulk Erase (128 Mbit) Electronic signature - JEDEC standard two-byte signature (2018h) More than 10000 Erase/Program cycles per sector More than 20-year data retention Packages - ECOPACK(R) (RoHS compliant)
SO16 (MF) 300 mils width VDFPN8 (ME) 8x6mm (MLP8)

December 2007
Rev 3
1/45
www.numonyx.com 1
Contents
M25P128
Contents
1 2 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 Serial data output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Serial data input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Serial clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Write Protect/Enhanced Program supply voltage (W/VPP) . . . . . . . . . . . . . 9 VCC supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3 4
SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 Page programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Sector Erase and Bulk Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Polling during a write, program or erase cycle . . . . . . . . . . . . . . . . . . . . . 12 Fast Program/Erase mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Active power and standby power modes . . . . . . . . . . . . . . . . . . . . . . . . . 13 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5 6
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.1 6.2 6.3 6.4 Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Read Identification (RDID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.4.1 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
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M25P128 6.4.2 6.4.3 6.4.4
Contents WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 BP2, BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.5 6.6 6.7 6.8 6.9 6.10
Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Read Data Bytes (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Read Data Bytes at Higher Speed (FAST_READ) . . . . . . . . . . . . . . . . . . 27 Page Program (PP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Sector Erase (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Bulk Erase (BE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7 8 9 10 11 12 13
Power-up and power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
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List of tables
M25P128
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Protected area sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Read Identification (RDID) data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Status Register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Power-Up Timing and VWI Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 VDFPN8 (MLP8), 8-lead Very thin Dual Flat Package No lead, 8 x 6mm, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 SO16 wide - 16 lead Plastic Small Outline, 300 mils body width . . . . . . . . . . . . . . . . . . . . 42 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
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M25P128
List of figures
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 VDFPN connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 SO connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Write Enable (WREN) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Write Disable (WRDI) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Read Identification (RDID) instruction sequence and data-out sequence . . . . . . . . . . . . . 21 Read Status Register (RDSR) instruction sequence and data-out sequence . . . . . . . . . . 23 Write Status Register (WRSR) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Read Data Bytes (READ) instruction sequence and data-out sequence . . . . . . . . . . . . . . 26 Read Data Bytes at Higher Speed (FAST_READ) instruction and data-out sequence . . . 27 Page Program (PP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Sector Erase (SE) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Bulk Erase (BE) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Power-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Write Protect setup and hold timing during WRSR when SRWD =1 . . . . . . . . . . . . . . . . . 39 Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 VPPH timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 VDFPN8 (MLP8), 8-lead Very thin Dual Flat Package No lead, 8x6mm, package outline . 41 SO16 wide - 16 lead Plastic Small Outline, 300 mils body width . . . . . . . . . . . . . . . . . . . . 42
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Summary description
M25P128
1
Summary description
The M25P128 is a 128 Mbit (16 Mbit x 8), multilevel Serial Flash memory, with advanced write protection mechanisms, accessed by a high speed SPI-compatible bus. The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction. The memory is organized as 64 sectors, each containing 1024 pages. Each page is 256 bytes wide. Thus, the whole memory can be viewed as consisting of 65536 pages, or 16777216 bytes. An enhanced Fast Program/Erase mode is available to speed up operations in factory environment. The device enters this mode whenever the VPPH voltage is applied to the Write Protect/Enhanced Program Supply Voltage pin (W/VPP). The whole memory can be erased using the Bulk Erase instruction, or a sector at a time, using the Sector Erase instruction. In order to meet environmental requirements, Numonyx offers these devices in ECOPACK(R) packages. ECOPACK(R) packages are Lead-free and RoHS compliant. Figure 1. Logic diagram
VCC
D C S W/VPP HOLD M25P128
Q
VSS
AI11313b
Table 1.
C D Q S W/VPP HOLD VCC VSS
Signal names
Serial Clock Serial Data Input Serial Data Output Chip Select Write Protect/Enhanced Program supply voltage Hold Supply Voltage Ground
6/45
M25P128 Figure 2. VDFPN connections
M25P128 S Q W/VPP VSS 1 2 3 4 8 7 6 5 VCC HOLD C D
Summary description
AI11314b
1. There is an exposed die paddle on the underside of the MLP8 package. This is pulled, internally, to VSS, and must not be allowed to be connected to any other voltage or signal line on the PCB. 2. See Package mechanical section for package dimensions, and how to identify pin-1.
Figure 3.
SO connections
M25P128 HOLD VCC DU DU DU DU S Q 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 C D DU DU DU DU VSS W/VPP
AI11315b
1. DU = Don't Use 2. See Package mechanical section for package dimensions, and how to identify pin-1.
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Signal description
M25P128
2
2.1
Signal description
Serial data output (Q)
This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (C).
2.2
Serial data input (D)
This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be programmed. Values are latched on the rising edge of Serial Clock (C).
2.3
Serial clock (C)
This input signal provides the timing of the serial interface. Instructions, addresses, or data present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on Serial Data Output (Q) changes after the falling edge of Serial Clock (C).
2.4
Chip Select (S)
When this input signal is High, the device is deselected and Serial Data Output (Q) is at high impedance. Unless an internal Program, Erase or Write Status Register cycle is in progress, the device will be in the Standby Power mode. Driving Chip Select (S) Low selects the device, placing it in the Active Power mode. After Power-up, a falling edge on Chip Select (S) is required prior to the start of any instruction.
2.5
Hold (HOLD)
The Hold (HOLD) signal is used to pause any serial communications with the device without deselecting the device. During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data Input (D) and Serial Clock (C) are Don't Care. To start the Hold condition, the device must be selected, with Chip Select (S) driven Low.
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M25P128
Signal description
2.6
Write Protect/Enhanced Program supply voltage (W/VPP)
W/VPP is both a control input and a power supply pin. The two functions are selected by the voltage range applied to the pin. If the W/VPP input is kept in a low voltage range (0V to VCC) the pin is seen as a control input. This input signal is used to freeze the size of the area of memory that is protected against program or erase instructions (as specified by the values in the BP2, BP1 and BP0 bits of the Status Register). If VPP is in the range of VPPH it acts as an additional power supply pin. In this case VPP must be stable until the Program/Erase algorithm is completed.
2.7
VCC supply voltage
VCC is the supply voltage.
2.8
VSS ground
VSS is the reference for the VCC supply voltage.
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SPI modes
M25P128
3
SPI modes
These devices can be driven by a microcontroller with its SPI peripheral running in either of the two following modes:

CPOL=0, CPHA=0 CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and output data is available from the falling edge of Serial Clock (C). The difference between the two modes, as shown in Figure 5, is the clock polarity when the bus master is in Stand-by mode and not transferring data:

C remains at 0 for (CPOL=0, CPHA=0) C remains at 1 for (CPOL=1, CPHA=1)
Figure 4.
Bus master and memory devices on the SPI bus
VSS VCC R(2) SDO
SPI Interface with (CPOL, CPHA) = (0, 0) or (1, 1)
SDI SCK CQD VCC VSS R(2) SPI memory device R(2) SPI memory device CQD VCC VSS R(2) SPI memory device CQD VCC VSS
SPI bus master
CS3
CS2
CS1 S W/VPP HOLD S W/VPP HOLD S W/VPP HOLD
AI12836
1. The Write Protect (W/VPP) and Hold (HOLD) signals should be driven, High or Low as appropriate. 2. These pull-up resistors, R, ensure that the memory devices are not selected if the Bus Master leaves the S line in the highimpedance state. As the Bus Master may enter a state where all inputs/outputs are in high impedance at the same time (e.g.: when the Bus Master is reset), the clock line (C) must be connected to an external pull-down resistor so that, when all inputs/outputs become high impedance, S is pulled High while C is pulled Low (thus ensuring that S and C do not become High at the same time, and so, that the tSHCH requirement is met).
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M25P128 Figure 5.
CPOL
SPI modes SPI modes supported
CPHA C
0
0
1
1
C
D
MSB
Q
MSB
AI01438B
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Operating features
M25P128
4
4.1
Operating features
Page programming
To program one data byte, two instructions are required: Write Enable (WREN), which is one byte, and a Page Program (PP) sequence, which consists of four bytes plus data. This is followed by the internal Program cycle (of duration tPP). To spread this overhead, the Page Program (PP) instruction allows up to 256 bytes to be programmed at a time (changing bits from 1 to 0), provided that they lie in consecutive addresses on the same page of memory. For optimized timings, it is recommended to use the Page Program (PP) instruction to program all consecutive targeted Bytes in a single sequence versus using several Page Program (PP) sequences with each containing only a few Bytes (see Section 6.8: Page Program (PP) and Table 14: AC characteristics).
4.2
Sector Erase and Bulk Erase
The Page Program (PP) instruction allows bits to be reset from 1 to 0. Before this can be applied, the bytes of memory need to have been erased to all 1s (FFh). This can be achieved either a sector at a time, using the Sector Erase (SE) instruction, or throughout the entire memory, using the Bulk Erase (BE) instruction. This starts an internal Erase cycle (of duration tSE or tBE). The Erase instruction must be preceded by a Write Enable (WREN) instruction.
4.3
Polling during a write, program or erase cycle
A further improvement in the time to Write Status Register (WRSR), Program (PP) or Erase (SE or BE) can be achieved by not waiting for the worst case delay (tW, tPP, tSE, or tBE). The Write In Progress (WIP) bit is provided in the Status Register so that the application program can monitor its value, polling it to establish when the previous Write cycle, Program cycle or Erase cycle is complete.
4.4
Fast Program/Erase mode
The Fast Program/Erase mode is used to speed up programming/erasing. The device enters the Fast Program/Erase mode during the Page Program, Sector Erase or Bulk Erase instruction whenever a voltage equal to VPPH is applied to the W/VPP pin. The use of the Fast Program/Erase mode requires specific operating conditions in addition to the normal ones (VCC must be within the normal operating range):

the voltage applied to the W/VPP pin must be equal to VPPH (see Table 10) ambient temperature, TA must be 25C 10C, the cumulated time during which W/VPP is at VPPH should be less than 80 hours
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M25P128
Operating features
4.5
Active power and standby power modes
When Chip Select (S) is Low, the device is selected, and in the Active Power mode. When Chip Select (S) is High, the device is deselected, but could remain in the Active Power mode until all internal cycles have completed (Program, Erase, Write Status Register). The device then goes in to the Standby Power mode. The device consumption drops to ICC1.
4.6
Status Register
The Status Register contains a number of status and control bits that can be read or set (as appropriate) by specific instructions. See Section 6.4: Read Status Register (RDSR) for a detailed description of the Status Register bits.
4.7
Protection modes
The environments where non-volatile memory devices are used can be very noisy. No SPI device can operate correctly in the presence of excessive noise. To help combat this, the M25P128 features the following data protection mechanisms:

Power On Reset and an internal timer (tPUW) can provide protection against inadvertent changes while the power supply is outside the operating specification. Program, Erase and Write Status Register instructions are checked that they consist of a number of clock pulses that is a multiple of eight, before they are accepted for execution. All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state by the following events: - - - - - - Power-up Write Disable (WRDI) instruction completion Write Status Register (WRSR) instruction completion Page Program (PP) instruction completion Sector Erase (SE) instruction completion Bulk Erase (BE) instruction completion

The Block Protect (BP2, BP1, BP0) bits allow part of the memory to be configured as read-only. This is the Software Protected Mode (SPM). The Write Protect (W/VPP) signal allows the Block Protect (BP2, BP1, BP0) bits and Status Register Write Disable (SRWD) bit to be protected. This is the Hardware Protected Mode (HPM).
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Operating features Table 2. Protected area sizes
Memory content Protected area none Upper 64th (1 Sector, 2Mb) Upper 32nd (2 Sectors, 4Mb) Upper 16nd (4 Sectors, 8Mb) Upper 8nd (8 Sectors, 16Mb)
M25P128
Status Register content BP2 Bit BP1 Bit BP0 Bit 0 0 0 0 1 1 1 1
1.
Unprotected area All Sectors (Sectors 0 to 63)(1) Sectors 0 to 62 Sectors 0 to 61 Sectors 0 to 59 Sectors 0 to 55
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
Upper Quarter (16 Sectors, 32Mb) Lower 3 Quarters (Sectors 0 to 47) Upper Half (32 Sectors, 64Mb) All sectors (64 Sectors, 128Mb) Lower Half (Sectors 0 to 31) none
The device is ready to accept a Bulk Erase instruction if, and only if, all Block Protect (BP2, BP1, BP0) are 0.
4.8
Hold condition
The Hold (HOLD) signal is used to pause any serial communications with the device without resetting the clocking sequence. However, taking this signal Low does not terminate any Write Status Register, Program or Erase cycle that is currently in progress. To enter the Hold condition, the device must be selected, with Chip Select (S) Low. The Hold condition starts on the falling edge of the Hold (HOLD) signal, provided that this coincides with Serial Clock (C) being Low (as shown in Figure 6). The Hold condition ends on the rising edge of the Hold (HOLD) signal, provided that this coincides with Serial Clock (C) being Low. If the falling edge does not coincide with Serial Clock (C) being Low, the Hold condition starts after Serial Clock (C) next goes Low. Similarly, if the rising edge does not coincide with Serial Clock (C) being Low, the Hold condition ends after Serial Clock (C) next goes Low. (This is shown in Figure 6). During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data Input (D) and Serial Clock (C) are Don't Care. Normally, the device is kept selected, with Chip Select (S) driven Low, for the whole duration of the Hold condition. This is to ensure that the state of the internal logic remains unchanged from the moment of entering the Hold condition. If Chip Select (S) goes High while the device is in the Hold condition, this has the effect of resetting the internal logic of the device. To restart communication with the device, it is necessary to drive Hold (HOLD) High, and then to drive Chip Select (S) Low. This prevents the device from going back to the Hold condition.
14/45
M25P128 Figure 6. Hold condition activation
Operating features
C
HOLD
Hold Condition (standard use)
Hold Condition (non-standard use)
AI02029D
15/45
Memory organization
M25P128
5
Memory organization
The memory is organized as:

16777216 bytes (8 bits each) 64 sectors (2 Mbits, 262144 bytes each) 65536 pages (256 bytes each).
Each page can be individually programmed (bits are programmed from 1 to 0). The device is Sector or Bulk Erasable (bits are erased from 0 to 1) but not Page Erasable. Figure 7. Block diagram
HOLD W/VPP S C D Q Control Logic
High Voltage Generator
I/O Shift Register
Address Register and Counter
256 Byte Data Buffer
Status Register
FFFFFFh
Y Decoder
Size of the read-only memory area
00000h 256 Bytes (Page Size) X Decoder
000FFh
AI11316b
16/45
M25P128 Table 3. Memory organization
Sector 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 FC0000h F80000h F40000h F00000h EC0000h E80000h E40000h E00000h DC0000h D80000h D40000h D00000h CC0000h C80000h C40000h C00000h BC0000h B80000h B40000h B00000h AC0000h A80000h A40000h A00000h 9C0000h 980000h 940000h 900000h 8C0000h 880000h 840000h 800000h 7C0000h 780000h 740000h Address Range
Memory organization
FFFFFFh FBFFFFh F7FFFFh F3FFFFh EFFFFFh EBFFFFh E7FFFFh E3FFFFh DFFFFFh DBFFFFh D7FFFFh D3FFFFh CFFFFFh CBFFFFh C7FFFFh C3FFFFh BFFFFFh BBFFFFh B7FFFFh B3FFFFh AFFFFFh ABFFFFh A7FFFFh A3FFFFh 9FFFFFh 9BFFFFh 97FFFFh 93FFFFh 8FFFFFh 8BFFFFh 87FFFFh 83FFFFh 7FFFFFh 7BFFFFh 77FFFFh
17/45
Memory organization Table 3. Memory organization (continued)
Sector 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 700000h 6C0000h 680000h 640000h 600000h 5C0000h 580000h 540000h 500000h 4C0000h 480000h 440000h 400000h 3C0000h 380000h 340000h 300000h 2C0000h 280000h 240000h 200000h 1C0000h 180000h 140000h 100000h 0C0000h 080000h 040000h 000000h Address Range 73FFFFh 6FFFFFh 6BFFFFh 67FFFFh 63FFFFh 5FFFFFh 5BFFFFh 57FFFFh 53FFFFh 4FFFFFh 4BFFFFh 47FFFFh 43FFFFh 3FFFFFh 3BFFFFh 37FFFFh 33FFFFh 2FFFFFh 2BFFFFh 27FFFFh 23FFFFh 1FFFFFh 1BFFFFh 17FFFFh 13FFFFh 0FFFFFh 0BFFFFh 07FFFFh 03FFFFh
M25P128
18/45
M25P128
Instructions
6
Instructions
All instructions, addresses and data are shifted in and out of the device, most significant bit first. Serial Data Input (D) is sampled on the first rising edge of Serial Clock (C) after Chip Select (S) is driven Low. Then, the one-byte instruction code must be shifted in to the device, most significant bit first, on Serial Data Input (D), each bit being latched on the rising edges of Serial Clock (C). The instruction set is listed in Table 4. Every instruction sequence starts with a one-byte instruction code. Depending on the instruction, this might be followed by address bytes, or by data bytes, or by both or none. In the case of a Read Data Bytes (READ), Read Data Bytes at Higher Speed (Fast_Read), Read Status Register (RDSR) or Read Identification (RDID) instruction, the shifted-in instruction sequence is followed by a data-out sequence. Chip Select (S) can be driven High after any bit of the data-out sequence is being shifted out. In the case of a Page Program (PP), Sector Erase (SE), Bulk Erase (BE), Write Status Register (WRSR), Write Enable (WREN) or Write Disable (WRDI), Chip Select (S) must be driven High exactly at a byte boundary, otherwise the instruction is rejected, and is not executed. That is, Chip Select (S) must driven High when the number of clock pulses after Chip Select (S) being driven Low is an exact multiple of eight. All attempts to access the memory array during a Write Status Register cycle, Program cycle or Erase cycle are ignored, and the internal Write Status Register cycle, Program cycle or Erase cycle continues unaffected. Table 4.
Instruction WREN WRDI RDID RDSR WRSR READ FAST_READ PP SE BE
Instruction set
Description Write Enable Write Disable Read Identification Read Status Register Write Status Register Read Data Bytes Read Data Bytes at Higher Speed Page Program Sector Erase Bulk Erase One-byte Instruction Code 0000 0110 0000 0100 1001 1111 0000 0101 0000 0001 0000 0011 0000 1011 0000 0010 1101 1000 1100 0111 06h 04h 9Fh 05h 01h 03h 0Bh 02h D8h C7h Address Dummy Bytes Bytes 0 0 0 0 0 3 3 3 3 0 0 0 0 0 0 0 1 0 0 0 Data Bytes 0 0 1 to 3 1 to 1 1 to 1 to 1 to 256 0 0
19/45
Instructions
M25P128
6.1
Write Enable (WREN)
The Write Enable (WREN) instruction (Figure 8) sets the Write Enable Latch (WEL) bit. The Write Enable Latch (WEL) bit must be set prior to every Page Program (PP), Sector Erase (SE), Bulk Erase (BE) and Write Status Register (WRSR) instruction. The Write Enable (WREN) instruction is entered by driving Chip Select (S) Low, sending the instruction code, and then driving Chip Select (S) High. Figure 8. Write Enable (WREN) instruction sequence
S 0 C Instruction D High Impedance Q
AI02281E
1
2
3
4
5
6
7
6.2
Write Disable (WRDI)
The Write Disable (WRDI) instruction (Figure 9) resets the Write Enable Latch (WEL) bit. The Write Disable (WRDI) instruction is entered by driving Chip Select (S) Low, sending the instruction code, and then driving Chip Select (S) High. The Write Enable Latch (WEL) bit is reset under the following conditions:

Power-up Write Disable (WRDI) instruction completion Write Status Register (WRSR) instruction completion Page Program (PP) instruction completion Sector Erase (SE) instruction completion Bulk Erase (BE) instruction completion Write Disable (WRDI) instruction sequence
S 0 C Instruction D High Impedance Q
AI03750D
Figure 9.
1
2
3
4
5
6
7
20/45
M25P128
Instructions
6.3
Read Identification (RDID)
The Read Identification (RDID) instruction allows the 8-bit manufacturer identification to be read, followed by two bytes of device identification. The manufacturer identification is assigned by JEDEC, and has the value 20h for Numonyx. The device identification is assigned by the device manufacturer, and indicates the memory type in the first byte (20h), and the memory capacity of the device in the second byte (18h). Any Read Identification (RDID) instruction while an Erase or Program cycle is in progress, is not decoded, and has no effect on the cycle that is in progress. The device is first selected by driving Chip Select (S) Low. Then, the 8-bit instruction code for the instruction is shifted in. This is followed by the 24-bit device identification, stored in the memory, being shifted out on Serial Data Output (Q), each bit being shifted out during the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 10. The Read Identification (RDID) instruction is terminated by driving Chip Select (S) High at any time during data output. When Chip Select (S) is driven High, the device is put in the Standby Power mode. Once in the Standby Power mode, the device waits to be selected, so that it can receive, decode and execute instructions. Table 5. Read Identification (RDID) data-out sequence
Device Identification Manufacturer Identification Memory Type 20h 20h Memory Capacity 18h
Figure 10. Read Identification (RDID) instruction sequence and data-out sequence
S 0 C Instruction D Manufacturer Identification High Impedance Q MSB 15 14 13 MSB
AI06809b
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18
28 29 30 31
Device Identification 3 2 1 0
21/45
Instructions
M25P128
6.4
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction allows the Status Register to be read. The Status Register may be read at any time, even while a Program, Erase or Write Status Register cycle is in progress. When one of these cycles is in progress, it is recommended to check the Write In Progress (WIP) bit before sending a new instruction to the device. It is also possible to read the Status Register continuously, as shown in Figure 11. Table 6.
b7 SRWD 0 0 BP2 BP1 BP0 WEL
Status Register format
b0 WIP
Status Register Write Protect Block Protect Bits Write Enable Latch Bit Write In Progress Bit
The status and control bits of the Status Register are as follows:
6.4.1
WIP bit
The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status Register, Program or Erase cycle. When set to 1, such a cycle is in progress, when reset to 0 no such cycle is in progress.
6.4.2
WEL bit
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write Status Register, Program or Erase instruction is accepted.
6.4.3
BP2, BP1, BP0 bits
The Block Protect (BP2, BP1, BP0) bits are non-volatile. They define the size of the area to be software protected against Program and Erase instructions. These bits are written with the Write Status Register (WRSR) instruction. When one or more of the Block Protect (BP2, BP1, BP0) bits is set to 1, the relevant memory area (as defined in Table 2) becomes protected against Page Program (PP) and Sector Erase (SE) instructions. The Block Protect (BP2, BP1, BP0) bits can be written provided that the Hardware Protected mode has not been set. The Bulk Erase (BE) instruction is executed if, and only if, all Block Protect (BP2, BP1, BP0) bits are 0.
6.4.4
SRWD bit
The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write Protect (W/VPP) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W/VPP) signal allow the device to be put in the Hardware Protected mode (when the Status Register Write Disable (SRWD) bit is set to 1, and Write Protect (W/VPP) is driven Low). In this mode, the non-volatile bits of the Status Register (SRWD, BP2, BP1, BP0) become
22/45
M25P128
Instructions read-only bits and the Write Status Register (WRSR) instruction is no longer accepted for execution. Figure 11. Read Status Register (RDSR) instruction sequence and data-out sequence
S 0 C Instruction D Status Register Out High Impedance Q 7 MSB 6 5 4 3 2 1 0 7 MSB
AI02031E
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
Status Register Out 6 5 4 3 2 1 0 7
23/45
Instructions
M25P128
6.5
Write Status Register (WRSR)
The Write Status Register (WRSR) instruction allows new values to be written to the Status Register. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded and executed, the device sets the Write Enable Latch (WEL). The Write Status Register (WRSR) instruction is entered by driving Chip Select (S) Low, followed by the instruction code and the data byte on Serial Data Input (D). The instruction sequence is shown in Figure 12. The Write Status Register (WRSR) instruction has no effect on b6, b5, b1 and b0 of the Status Register. b6 and b5 are always read as 0. Chip Select (S) must be driven High after the eighth bit of the data byte has been latched in. If not, the Write Status Register (WRSR) instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed Write Status Register cycle (whose duration is tW) is initiated. While the Write Status Register cycle is in progress, the Status Register may still be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed. When the cycle is completed, the Write Enable Latch (WEL) is reset. The Write Status Register (WRSR) instruction allows the user to change the values of the Block Protect (BP2, BP1, BP0) bits, to define the size of the area that is to be treated as read-only, as defined in Table 2. The Write Status Register (WRSR) instruction also allows the user to set or reset the Status Register Write Disable (SRWD) bit in accordance with the Write Protect (W/VPP) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W/VPP) signal allow the device to be put in the Hardware Protected Mode (HPM). The Write Status Register (WRSR) instruction is not executed once the Hardware Protected Mode (HPM) is entered. Table 7.
W/VPP Signal 1 0 1
Protection modes
SRWD Bit 0 0 1 Mode Write Protection of the Status Register Memory Content Protected Area(1) Unprotected Area(1)
Status Register is Writable (if the WREN instruction Software has set the WEL bit) Protected (SPM) The values in the SRWD, BP2, BP1 and BP0 bits can be changed Status Register is Hardware Hardware write protected Protected The values in the SRWD, (HPM) BP2, BP1 and BP0 bits cannot be changed
Protected against Page Program, Sector Erase and Bulk Erase
Ready to accept Page Program and Sector Erase instructions
0
1
Protected against Page Program, Sector Erase and Bulk Erase
Ready to accept Page Program and Sector Erase instructions
1. As defined by the values in the Block Protect (BP2, BP1, BP0) bits of the Status Register, as shown in Table 2: Protected area sizes.
The protection features of the device are summarized in Table 7 When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial delivery state), it is possible to write to the Status Register provided that the Write Enable
24/45
M25P128
Instructions Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless of the whether Write Protect (W/VPP) is driven High or Low. When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two cases need to be considered, depending on the state of Write Protect (W/VPP):
If Write Protect (W/VPP) is driven High, it is possible to write to the Status Register provided that the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction. If Write Protect (W/VPP) is driven Low, it is not possible to write to the Status Register even if the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction. (Attempts to write to the Status Register are rejected, and are not accepted for execution). As a consequence, all the data bytes in the memory area that are software protected (SPM) by the Block Protect (BP2, BP1, BP0) bits of the Status Register, are also hardware protected against data modification.
Regardless of the order of the two events, the Hardware Protected Mode (HPM) can be entered:

by setting the Status Register Write Disable (SRWD) bit after driving Write Protect (W/VPP) Low or by driving Write Protect (W/VPP) Low after setting the Status Register Write Disable (SRWD) bit.
The only way to exit the Hardware Protected Mode (HPM) once entered is to pull Write Protect (W/VPP) High. If Write Protect (W/VPP) is permanently tied High, the Hardware Protected Mode (HPM) can never be activated, and only the Software Protected Mode (SPM), using the Block Protect (BP2, BP1, BP0) bits of the Status Register, can be used. Figure 12. Write Status Register (WRSR) instruction sequence
S 0 C Instruction Status Register In 7 High Impedance Q
AI02282D
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
D
6
5
4
3
2
1
0
MSB
25/45
Instructions
M25P128
6.6
Read Data Bytes (READ)
The device is first selected by driving Chip Select (S) Low. The instruction code for the Read Data Bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that address, is shifted out on Serial Data Output (Q), each bit being shifted out, at a maximum frequency fR, during the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 13. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single Read Data Bytes (READ) instruction. When the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely. The Read Data Bytes (READ) instruction is terminated by driving Chip Select (S) High. Chip Select (S) can be driven High at any time during data output. Any Read Data Bytes (READ) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 13. Read Data Bytes (READ) instruction sequence and data-out sequence
S 0 C Instruction 24-Bit Address 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
D High Impedance Q
23 22 21 MSB
3
2
1
0 Data Out 1 7 6 5 4 3 2 1 0 Data Out 2 7
MSB
AI03748D
26/45
M25P128
Instructions
6.7
Read Data Bytes at Higher Speed (FAST_READ)
The device is first selected by driving Chip Select (S) Low. The instruction code for the Read Data Bytes at Higher Speed (FAST_READ) instruction is followed by a 3-byte address (A23A0) and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that address, is shifted out on Serial Data Output (Q), each bit being shifted out, at a maximum frequency fC, during the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 14. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single Read Data Bytes at Higher Speed (FAST_READ) instruction. When the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely. The Read Data Bytes at Higher Speed (FAST_READ) instruction is terminated by driving Chip Select (S) High. Chip Select (S) can be driven High at any time during data output. Any Read Data Bytes at Higher Speed (FAST_READ) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 14. Read Data Bytes at Higher Speed (FAST_READ) instruction and data-out sequence
S 0 C Instruction 24 BIT ADDRESS 1 2 3 4 5 6 7 8 9 10 28 29 30 31
D High Impedance Q
23 22 21
3
2
1
0
S 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 C Dummy Byte
D
7
6
5
4
3
2
1
0 DATA OUT 1 DATA OUT 2 1 0 7 MSB 6 5 4 3 2 1 0 7 MSB
AI04006
Q
7 MSB
6
5
4
3
2
27/45
Instructions
M25P128
6.8
Page Program (PP)
The Page Program (PP) instruction allows bytes to be programmed in the memory (changing bits from 1 to 0). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). The Page Program (PP) instruction is entered by driving Chip Select (S) Low, followed by the instruction code, three address bytes and at least one data byte on Serial Data Input (D). If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page (from the address whose 8 least significant bits (A7-A0) are all zero). Chip Select (S) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 15. If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If less than 256 Data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page. For optimized timings, it is recommended to use the Page Program (PP) instruction to program all consecutive targeted Bytes in a single sequence versus using several Page Program (PP) sequences with each containing only a few Bytes (see Table 14: AC characteristics). Chip Select (S) must be driven High after the eighth bit of the last data byte has been latched in, otherwise the Page Program (PP) instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed Page Program cycle (whose duration is tPP) is initiated. While the Page Program cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Page Program (PP) instruction applied to a page which is protected by the Block Protect (BP2, BP1, BP0) bits (see Table 2 and Table 3) is not executed.
28/45
M25P128 Figure 15. Page Program (PP) instruction sequence
S 0 C Instruction 24-Bit Address Data Byte 1 1 2 3 4 5 6 7 8 9 10
Instructions
28 29 30 31 32 33 34 35 36 37 38 39
D
23 22 21 MSB
3
2
1
0
7
6
5
4
3
2
1
0
MSB
S
2072 2073 2074 2075 2076 2077 2078
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 C Data Byte 2 Data Byte 3
Data Byte 256
D
7
6
5
4
3
2
1
0
7 MSB
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
AI04082B
MSB
MSB
2079
29/45
Instructions
M25P128
6.9
Sector Erase (SE)
The Sector Erase (SE) instruction sets to 1 (FFh) all bits inside the chosen sector. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). The Sector Erase (SE) instruction is entered by driving Chip Select (S) Low, followed by the instruction code, and three address bytes on Serial Data Input (D). Any address inside the Sector (see Table 3) is a valid address for the Sector Erase (SE) instruction. Chip Select (S) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 16. Chip Select (S) must be driven High after the eighth bit of the last address byte has been latched in, otherwise the Sector Erase (SE) instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed Sector Erase cycle (whose duration is tSE) is initiated. While the Sector Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Sector Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Sector Erase (SE) instruction applied to a page which is protected by the Block Protect (BP2, BP1, BP0) bits (see Table 2 and Table 3) is not executed. Figure 16. Sector Erase (SE) instruction sequence
S 0 C Instruction 24 Bit Address 1 2 3 4 5 6 7 8 9 29 30 31
D
23 22 MSB
2
1
0
AI03751D
30/45
M25P128
Instructions
6.10
Bulk Erase (BE)
The Bulk Erase (BE) instruction sets all bits to 1 (FFh). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). The Bulk Erase (BE) instruction is entered by driving Chip Select (S) Low, followed by the instruction code on Serial Data Input (D). Chip Select (S) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 17. Chip Select (S) must be driven High after the eighth bit of the instruction code has been latched in, otherwise the Bulk Erase instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed Bulk Erase cycle (whose duration is tBE) is initiated. While the Bulk Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Bulk Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. The Bulk Erase (BE) instruction is executed only if all Block Protect (BP2, BP1, BP0) bits are 0. The Bulk Erase (BE) instruction is ignored if one, or more, sectors are protected. Figure 17. Bulk Erase (BE) instruction sequence
S 0 C Instruction D 1 2 3 4 5 6 7
AI03752D
31/45
Power-up and power-down
M25P128
7
Power-up and power-down
At Power-up and Power-down, the device must not be selected (that is Chip Select (S) must follow the voltage applied on VCC) until VCC reaches the correct value:

VCC(min) at Power-up, and then for a further delay of tVSL VSS at Power-down
Usually a simple pull-up resistor on Chip Select (S) can be used to ensure safe and proper Power-up and Power-down. To avoid data corruption and inadvertent write operations during Power-up, a Power On Reset (POR) circuit is included. The logic inside the device is held reset while VCC is less than the Power On Reset (POR) threshold voltage, VWI - all operations are disabled, and the device does not respond to any instruction. Moreover, the device ignores all Write Enable (WREN), Page Program (PP), Sector Erase (SE), Bulk Erase (BE) and Write Status Register (WRSR) instructions until a time delay of tPUW has elapsed after the moment that VCC rises above the VWI threshold. However, the correct operation of the device is not guaranteed if, by this time, VCC is still below VCC(min). No Write Status Register, Program or Erase instructions should be sent until the later of:

tPUW after VCC passed the VWI threshold tVSL after VCC passed the VCC(min) level
These values are specified in Table 8. If the delay, tVSL, has elapsed, after VCC has risen above VCC(min), the device can be selected for READ instructions even if the tPUW delay is not yet fully elapsed. At Power-up, the device is in the following state:

The device is in the Standby Power mode The Write Enable Latch (WEL) bit is reset.
Normal precautions must be taken for supply rail decoupling, to stabilize the VCC supply. Each device in a system should have the VCC rail decoupled by a suitable capacitor close to the package pins. (Generally, this capacitor is of the order of 0.1F). At Power-down, when VCC drops from the operating voltage, to below the Power On Reset (POR) threshold voltage, VWI, all operations are disabled and the device does not respond to any instruction. (The designer needs to be aware that if a Power-down occurs while a Write, Program or Erase cycle is in progress, some data corruption can result.) Power up sequencing for Fast program/erase mode: VCC should attain VCCMIN before VPPH is applied.
32/45
M25P128 Figure 18. Power-up timing
VCC VCC(max) Program, Erase and Write Commands are Rejected by the Device Chip Selection Not Allowed VCC(min) Reset State of the Device VWI tPUW tVSL
Initial delivery state
Read Access allowed
Device fully accessible
time
AI04009C
Table 8.
Symbol tVSL(1) tPUW(1) VWI
Power-Up Timing and VWI Threshold
Parameter VCC(min) to S Low Time delay to Write instruction Write Inhibit Voltage Min. 60 1 1.5 10 2.5 Max. Unit s ms V
1. These parameters are characterized only.
8
Initial delivery state
The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status Register contains 00h (all Status Register bits are 0).
33/45
Maximum rating
M25P128
9
Maximum rating
Stressing the device outside the ratings listed in Table 9 may cause permanent damage to the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the Operating sections of this specification, is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the Numonyx SURE Program and other relevant quality documents. Table 9.
Symbol TSTG VIO VCC VPP VESD Storage Temperature Input and output voltage (with respect to Ground) Supply voltage Fast Program/Erase voltage Electrostatic Discharge Voltage (Human Body Model)
(1)
Absolute maximum ratings
Parameter Min. -65 -0.5 -0.2 -0.2 -2000 Max. 150 VCC + 0.6 4.0 10.0 2000 Unit C V V V V
1. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 , R2=500 )
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M25P128
DC and AC parameters
10
DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC Characteristic tables that follow are derived from tests performed under the Measurement Conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. Table 10.
Symbol VCC VPPH TA TAVPP Supply Voltage Supply Voltage on W/VPP pin for Fast Program/Erase mode Ambient Operating Temperature Ambient Operating Temperature for Fast Program/Erase mode
Operating conditions
Parameter Min. 2.7 8.5 -40 15 25 Typ. Max. 3.6 9.5 85 35 Unit V V C C
Table 11.
Symbol CL
AC measurement conditions
Parameter Load Capacitance Input Rise and Fall Times Input Pulse Voltages Input Timing Reference Voltages Output Timing Reference Voltages Min. 30 5 0.2VCC to 0.8VCC 0.3VCC to 0.7VCC VCC / 2 Max. Unit pF ns V V V
1. Output Hi-Z is defined as the point where data out is no longer driven.
Figure 19. AC measurement I/O waveform
Input Levels 0.8VCC Input and Output Timing Reference Levels 0.7VCC 0.5VCC 0.3VCC
AI07455
0.2VCC
Table 12.
Symbol COUT CIN
Capacitance
Parameter Output Capacitance (Q) Input Capacitance (other pins) Test Condition VOUT = 0V VIN = 0V Min. Max. 8 6 Unit pF pF
1. Sampled only, not 100% tested, at TA=25C and a frequency of 20 MHz.
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DC and AC parameters Table 13.
Symbol ILI ILO ICC1
M25P128 DC characteristics
Parameter Test Condition (in addition to those in Table 10) Min. Max. 2 2 S = VCC, VIN = VSS or VCC C = 0.1VCC / 0.9.VCC at 50MHz, Q = open 100 8 4 20 20 20 20 20 20 - 0.5 0.7VCC IOL = 1.6mA
IOH
Unit A A A mA mA mA mA mA mA mA mA V V V V
Input Leakage Current Output Leakage Current Standby Current
ICC3
Operating Current (READ) C = 0.1VCC / 0.9.VCC at 20MHz, Q = open Operating Current (PP) Operating Current (WRSR) Operating Current (SE) Operating Current (BE) Operating current for Fast Program/Erase mode VPP Operating current in Fast Program/Erase mode Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage S = VCC S = VCC S = VCC S = VCC S = VCC, VPP = VPPH S = VCC, VPP = VPPH
ICC4 ICC5 ICC6 ICC7 ICCPP(1) IPP(1) VIL VIH VOL VOH
0.3VCC VCC+0.2 0.4
= -100A
VCC-0.2
1. Characterized only.
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M25P128 Table 14. AC characteristics
DC and AC parameters
Test conditions specified in Table 10 and Table 11 Symbol fC fR tCH tCL
(1)
Alt. fC
Parameter Clock Frequency for the following instructions: FAST_READ, PP, SE, BE, WREN, WRDI, RDID, RDSR, WRSR Clock Frequency for READ instructions
Min. D.C. D.C. 9 9 0.1 0.1 5 5 2 5 5 5 100
Typ.
Max. 50 20
Unit MHz MHz ns ns V/ns V/ns ns ns ns ns ns ns ns
tCLH tCLL
Clock High Time Clock Low Time Clock Rise Time(3) (peak to peak) Clock Fall Time(3) (peak to peak)
(1)
tCLCH(2) tCHCL(2) tSLCH tCHSL tDVCH tCHDX tCHSH tSHCH tSHSL tSHQZ
(2)
tCSS
S Active Setup Time (relative to C) S Not Active Hold Time (relative to C)
tDSU tDH
Data In Setup Time Data In Hold Time S Active Hold Time (relative to C) S Not Active Setup Time (relative to C)
tCSH tDIS tV tHO
S Deselect Time Output Disable Time Clock Low to Output Valid Output Hold Time HOLD Setup Time (relative to C) HOLD Hold Time (relative to C) HOLD Setup Time (relative to C) HOLD Hold Time (relative to C)
8 8 0 5 5 5 5 8 8 20 100 200 5 2.5 2.5 1.2(2) 2 1.6(2) 6 7 15
ns ns ns ns ns ns ns ns ns ns ns ns ms
tCLQV tCLQX tHLCH tCHHH tHHCH tCHHL tHHQX(2) tHLQZ(2) tWHSL(4) tSHWL
(4)
tLZ tHZ
HOLD to Output Low-Z HOLD to Output High-Z Write Protect Setup Time Write Protect Hold Time Enhanced Program Supply Voltage High to Chip Select Low Write Status Register Cycle Time Page Program Cycle Time (256 Bytes)
tVPPHSL(2)(5) tW
tPP(6)
Page Program Cycle Time (n Bytes) Page Program Cycle Time (VPP = VPPH) (256 Bytes) Sector Erase Cycle Time
ms
tSE
s
Sector Erase Cycle Time (VPP = VPPH)
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DC and AC parameters Table 14. AC characteristics (continued)
Test conditions specified in Table 10 and Table 11 Symbol tBE Alt. Parameter Bulk Erase Cycle Time Bulk Erase Cycle Time (VPP = VPPH) Min. Typ. 105 56(2)
M25P128
Max. 250
Unit s
1. tCH and tCL must be greater than or equal to 1/fC (max). 2. Value is guaranteed by characterization, not 100% tested in production. 3. Expressed as a slew-rate. 4. Only applicable as a constraint for WRSR instruction when SRWD is set to 1. 5. VPPH should be kept at a valid level until the program or erase operation has completed and its result (success or failure) is known. 6. Due to the Multi Level Cell technology, when using the Page Program (PP) instruction to program consecutive Bytes, optimized timings are obtained with one sequence including all the Bytes versus several sequences of only a few Bytes. If only a single byte is programmed, the estimated programming time is close to the time needed to program a full page of 256 Bytes. Therefore, it is highly recommended to use the Page Program (PP) instruction with a sequence of 256 consecutive Bytes. (1 n 256)
Figure 20. Serial input timing
tSHSL S tCHSL C tDVCH tCHDX D MSB IN tCLCH LSB IN tCHCL tSLCH tCHSH tSHCH
Q
High Impedance
AI01447C
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M25P128
DC and AC parameters
Figure 21. Write Protect setup and hold timing during WRSR when SRWD =1
W/VPP tWHSL
tSHWL
S
C
D High Impedance Q
AI07439b
Figure 22. Hold timing
S tHLCH tCHHL C tCHHH tHLQZ Q tHHQX tHHCH
D
HOLD
AI02032
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DC and AC parameters Figure 23. Output timing
S tCH C tCLQV tCLQX Q tQLQH tQHQL D
ADDR.LSB IN
M25P128
tCLQV tCLQX
tCL
tSHQZ
LSB OUT
AI01449e
Figure 24. VPPH timing
End of PP, SE or BE (identified by WPI polling)
S
C
D
PP, SE, BE
VPPH W/VPP
tVPPHSL ai12092
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M25P128
Package mechanical
11
Package mechanical
Figure 25. VDFPN8 (MLP8), 8-lead Very thin Dual Flat Package No lead, 8x6mm, package outline
D
E
E2
e
b A L ddd A1
VDFPN-02
D2 L1
1. Drawing is not to scale. 2. The circle in the top view of the package indicates the position of pin 1.
Table 15.
VDFPN8 (MLP8), 8-lead Very thin Dual Flat Package No lead, 8 x 6mm, package mechanical data
millimeters inches Max. 1.00 0.00 0.40 8.00 6.40
(1)
Symbol Typ. A A1 b D D2 ddd E E2 e K L L1 N 8 0.50 6.00 4.80 1.27 - 0.20 0.45 0.60 0.15 8 0.0197 - 0.85 Min. Typ. 0.0335 0.0000 0.0157 0.3150 0.2520 0.0020 0.2362 0.1890 0.0500 - 0.0079 0.0177 0.0236 0.0059 - 0.0138 Min. Max. 0.0394 0.0020 0.0189
0.05 0.48
0.35
0.05
1. D2 Max should not exceed (D - K - 2 x L).
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Package mechanical Figure 26. SO16 wide - 16 lead Plastic Small Outline, 300 mils body width
M25P128
D
16 9
h x 45
C E H
1
8
A2 A ddd A1 L
B SO-H
e
1. Drawing is not to scale.
Table 16.
Symbol
SO16 wide - 16 lead Plastic Small Outline, 300 mils body width
millimeters Typ Min 2.35 0.10 0.33 0.23 10.10 7.40 1.27 - 10.00 0.25 0.40 0 Max 2.65 0.30 0.51 0.32 10.50 7.60 - 10.65 0.75 1.27 8 0.10 0.050 Typ inches Min 0.093 0.004 0.013 0.009 0.398 0.291 - 0.394 0.010 0.016 0 Max 0.104 0.012 0.020 0.013 0.413 0.299 - 0.419 0.030 0.050 8 0.004
A A1 B C D E e H h L ddd
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M25P128
Part numbering
12
Part numbering
Table 17.
Example:
Ordering information scheme
M25P128 - V MF 6 T P
Device Type M25P = Serial Flash Memory for Code Storage
Device Function 128 = 128 Mit (16 Mb x 8)
Operating Voltage V = VCC = 2.7 to 3.6 V
Package MF = SO16 (300 mil width) ME = VDFPN8 8x6mm (MLP8)
Device Grade 6 = Industrial temperature range, -40 to 85 C. Device tested with standard test flow
Option blank = Standard Packing T = Tape and Reel Packing
Plating Technology P or G = ECOPACK(R) (RoHs compliant)
For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest Numonyx Sales Office. The category of second-Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label.
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Revision history
M25P128
13
Revision history
Table 18.
Date 02-May-2005 09-Jun-2005
Document revision history
Revision 0.1 0.2 First issue. Table 2: Protected area sizes updated. Memory capacity modified in Section 6.3: Read Identification (RDID). Updated tPP values in Table 14: AC characteristics and tVSL value in Table 8: Power-Up Timing and VWI Threshold. Modified information in Section 4.1: Page programming and Section 6.8: Page Program (PP). Document status promoted from Target specification to Preliminary data. Packages are ECOPACK(R) compliant. Blank option removed under Plating Technology in Table 17. Read Electronic Signature (RES) instruction removed. ICC1 parameter updated in Table 13: DC characteristics. Document status promoted from Preliminary Data to full Datasheet. Write Protect pin (W) changed to Write Protect/Enhanced Program supply voltage (W/VPP). Section 4.4: Fast Program/Erase mode and Figure 24: VPPH timing added. Power-up specified for Fast Program/Erase mode in Power-up and power-down section. Figure 4: Bus master and memory devices on the SPI bus modified and Note 2 added. Note 1 added below Table 15: VDFPN8 (MLP8), 8-lead Very thin Dual Flat Package No lead, 8 x 6mm, package mechanical data. VIO max modified in Table 9: Absolute maximum ratings. Applied Numonyx branding. Changes
28-Aug-2005
0.3
20-Jan-2006
1
17-Oct-2006
2
10-Dec-2007
3
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M25P128
Please Read Carefully:
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYXTM PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. Numonyx may make changes to specifications and product descriptions at any time, without notice. Numonyx, B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Numonyx reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting Numonyx's website at http://www.numonyx.com. Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright (c) 11/5/7, Numonyx, B.V., All Rights Reserved.
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